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Design Principle and Static Coding Efficiency of STT-Coder: A Table-Driven Arithmetic Coder

Ikuro Ueno and Fumitaka Ono
Graduate School, Tokyo Polytechnic University, Kanagawa, Japan
Abstract—We have proposed the concept of simple and fast binary arithmetic coder, STT-coder, in which arithmetic operation can be executed by referring a state transition table just like the case of Huffman coding. In our previous study, STT-coder with 3-bit interval register was designed and evaluated. Its coding efficiency was found to be satisfactory despite of the introduction of the simplification of the process. Then we have been trying to extend the register to 6-bit length in order to improve the performance of higher MPS probability sources. In this paper, we introduce a coding parameter of STT-coder, which is called as offset, and optimize the value to maximize the average coding efficiency. We further tried to enlarge the expected interval size after the renormalization to improve the coding efficiency of higher MPS probability sources by sacrificing the accuracy of interval division ratio in low MPS probability sources, which turned out to improve the coding efficiency in total.

Index Terms—image compression, arithmetic coding, entropy, coding efficiency

Cite: Ikuro Ueno and Fumitaka Ono, "Design Principle and Static Coding Efficiency of STT-Coder: A Table-Driven Arithmetic Coder," International Journal of Signal Processing Systems, Vol. 1, No. 2, pp. 177-182, December 2013. doi: 10.12720/ijsps.1.2.177-182

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