Abstract—In this paper, area and power efficient design of interleaver/deinterleaver for IEEE 802.16 (WiMAX) networks is presented. Interleaving plays an important role in wireless networks in combating burst errors. It spreads burst error among multiple code words, thus reduces erroneous bits per code word symbol which can be corrected by forward error correction (FEC) decoder. The paper proposes an efficient hardware design that avoids look-up table (LUT) ROM and complex address generator logic. It uses only simple linear address generator circuit and multiplexer (MUX) based efficient intra-column permutation logic. The design supports all modulation schemes and sub-channelization. ASIC implementation results reveal that total number of gate count for interleaver is 25.9k and for deinterleaver is 26.1k. The combined system takes core chip area of 1.11mm2 and consumes power of 0.586mW at 5MHz frequency. 
 

Index Terms—burst-error, interleaving, permutation, WiMAX

Cite: Zuber M. Patel, "Power and Area Efficient Hardware Architecture for WiMAX Interleaving," International Journal of Signal Processing Systems, Vol. 3, No. 1, pp. 60-64, June 2015. doi: 10.12720/ijsps.3.1.60-64