Abstract—Today’s complex SOC solutions demand low power processors. Synchronous processors which consume more than 40 % of power in clock circuitry are being conveniently replaced by low power delay-insensitive (DI) asynchronous logic. In this paper, a Micro-pipelined GALS based 2D Fast Fourier Transform [FFT] Processor is designed and implemented to perform power, area and timing analysis. The implemented design has given power advantage of 78.22% and timing advantage of 39.99% when compared with similar synchronous 2D FFT processor. The design is a synthesizable core which can be extended to be part of Complex DSP architecture and hence is a right choice for any MPSOC design.

 

Index Terms—system on chip [SoC], delay insensitive [DI], 2D fast fourier transform, micro pipelined, globally asynchronous and locally synchronous [GALS], synthesizable core, MPSoC

Cite: Y. J. M. Shirur and V. S. Chakravarthi, "Design and Implementation of Power Efficient Micro Pipelined GALS Based 2-D FFT Processor Core," International Journal of Signal Processing Systems, Vol. 3, No. 2, pp. 166-171, December 2015. doi: 10.12720/ijsps.3.2.166-171