Abstract—This paper presents a Digital Signal Processing (DSP) technique to compensate nonlinearities in reconfigurable Sigma Delta (ΣΔ) Modulator. In order to design digitally enhanced transceiver, a problem of nonlinearities in these modulators should be addressed. The problem arises due to the constituent building block of ΣΔ Modulators i.e. Digital to Analog Converter (DAC). Since DAC is outside the ΣΔ signal path; the nonlinearities are not reduced by over-sampled quantization and shaping. In this paper, the nonlinearity effects of ΣΔ Modulator are captured by simulating the Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio (SNDR), and Spurious Free Dynamic Range (SFDR). For correction, the nonlinearity affected samples are passed to a transversal filter where sample-by-sample compensation is done using the simulated ideal response as a reference. The Normalized Least Mean Square (NLMS) algorithm is employed to adjust and update the filter tap-weights. Simulation results show that for a three-tone input to 4-bit first order ΣΔ Modulator, the SNDR and SFDR improves by 24.6 dB and 34 dB respectively.

Index Terms—ΣΔ modulators, NLMS, nonlinearity, compensation, sigma delta ADC, digital assisted analog circuit, non-linearity correction

Cite: Atta Ul Mustafa, Muhammad Atif, and Rashad Ramzan, "Compensation of Nonlinearities in ΣΔ Modulators Using Digital Assisted Analog Electronics Approach," International Journal of Signal Processing Systems, Vol. 2, No. 1, pp. 55-59, June 2014. doi: 10.12720/ijsps.2.1.55-59