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Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

P. Upadhyay 1, R. Kar2, D. Mandal 2, and S. P. Ghoshal 2
1. ECE Department, Maharishi Markandeshwar University, Solan Himachal Pradesh, India-173229
2. National Institute of Technology, Durgapur, West Bengal, India-713209
Abstract—This paper presents the analysis of dynamic noise margin of proposed 8T static random access memory (SRAM) cell. The proposed SRAM cell has two voltage sources, one connected to the bit line and the other is connected to bitbar line. These voltage sources are used to reduce the swing voltage at the output nodes. This reduction of swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell during switching activity. The dynamic noise margin (DNM) analysis is carried out and the results are compared with those of conventional 6T SRAM cell and existing 10T SRAM cell for different word line pulse widths. The proposed SRAM cell has higher value of DNM which ensures the higher stability than 6T and 10T SRAM cells. Simulation has been done in 65nm environment with a power supply of 1V. Microwind 3.1 is used for simulation purpose.

Index Terms—CMOS, dynamic power, dynamic noise margin, pulse width, sram, voltage swing, word line

Cite: P. Upadhyay, R. Kar, D. Mandal, and S. P. Ghoshal, "Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation," International Journal of Signal Processing Systems, Vol. 1, No. 2, pp. 136-140, December 2013. doi: 10.12720/ijsps.1.2.136-140
 

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